Fault Injection for Logic Synthesis Design using VHDL

Fault injection provides a method of assessing the dependability of a system under test. Traditionally fault injection is employed near the end of the design process after hardware and software prototypes have been developed. In order to eliminate costly re-designs near the end of the design process, a methodology for performing fault injection throughout the design process is described in this paper. This methodology incorporates a fault injection technique that can be used with any VHDL model, including behavioral, synthesizeable VHDL models. The technique separates the fault-free VHDL descriptions from the fault injection process so that existing models can be used with minimal changes to the existing VHDL code. The fault injection is accomplished through the use of an alternate definition of the Mentor Graphics standard bit type, qsim_state, so that fault injection can be performed on the same VHDL model that is synthesized using Autologic. Also, the same fault injection technique can be used on a structural VHDL model of the synthesized design generated using the Mentor Graphics utility, vhdlwrite. The fault injection methodology is applied to the design of a watchdog monitor card in a distributed computer system. Simulation results illustrate the fault injection methodology at multiple levels.